Method for Forming a PN Junction and Associated Semiconductor Device

ABSTRACT

An integrated circuit includes an insulating layer overlying a semiconductor substrate. A semiconductor layer of a first conductivity type overlies the insulating layer. A plurality of projecting regions that are spaced apart from each other overly the semiconductor layer. A sequence of PN junctions are in the semiconductor layer. Each PN junction is located at an edge of an associated projecting region. Each PN junction also extends vertically from an upper surface of the semiconductor layer to the insulating layer.

This application is a divisional of U.S. patent application Ser. No. 15/364,603, filed Nov. 30, 2016, and entitled “Method for Forming a PN Junction and Associated Semiconductor Device,” which claims priority to French Application No. 1654897 filed May 31, 2016, both applications are incorporated herein by reference in their entirety.

TECHNICAL FIELD

Embodiments of the invention relate to a method for forming a PN junction and an associated semiconductor device. For example, the method could be used for manufacturing a substrate isolated p-n power diode using floating-gate nonvolatile memory technology.

BACKGROUND

FIG. 1 shows an electronic circuit CI suitable for a contactless application including a diode bridge DBr (typically a Graetz bridge) for delivering a direct current voltage VDC from the voltage present at the terminals AC₀ and AC₁ of the antenna ANT₁ of the circuit, coupled to the antenna ANT₂ of a reader RD.

In this application, the circuit CI includes a latch circuit LTC, conventionally having four transistors T₂-T₅, adapted to store a digital data element. A reset transistor T₁ is also shown, and is controlled by a signal TX delivered by the circuit's processing means COM.

The latch LTC is formed in a box structure N-ISO, itself formed in a semiconductor substrate PSUB. The transistors T₁-T₃ are formed in a box structure PW, itself formed in the box structure N-ISO. The interfaces between the differently doped box structures form diodes Dpwniso and Dnisopsub.

A current flows in the antenna ANT₁ in a direction representative of the data element stored in the latch LTC, so that this element can be read by the reader RD.

The diodes of the bridge DBr, based on polycrystalline silicon, also called polysilicon, are usually formed directly in the substrate PSUB, or in the box structure N-ISO, and this may introduce undesirable bipolar effects.

In fact, recurrent problems have been encountered in the use of diodes whose doped regions are directly implanted in the substrate. These undesirable effects are, for example, due to parasitic PN junctions, and are usually seen in the starting or latching of the circuit.

It is desirable to avoid these parasitic effects in a way which is simple and compatible with non-volatile memory technology.

On the other hand, some dopant diffusion processes in the usual diode manufacturing methods are poorly controlled, for example because of masks requiring strict alignment which is difficult to establish, the defects in this alignment resulting in unpredictability of the characteristics of the diodes.

SUMMARY

Modes of construction and embodiment of the invention relate to PN junction diodes, and more particularly to polycrystalline silicon-based diodes used, for example, to form a bridge rectifier (Graetz bridge) in integrated circuits for use, notably, in contactless telecommunications technologies and incorporating, for example, non-volatile memories.

According to one aspect, a method for manufacturing a plurality of diodes comprises a first implantation of dopants having a second type of conductivity, of the P-type for example, in a first semiconductor layer having a first type of conductivity, of the N-type for example, located on an insulating layer covering a semiconductor substrate and surmounted by projecting regions spaced apart from each other, so as to form a sequence of PN junctions forming the diodes in the first semiconductor layer extending to the insulating layer at the edge of the projecting regions.

The projecting regions, which may advantageously be formed in combination with the forming of floating gates of floating-gate transistors of a non-volatile memory, thus serve as a hard mask for implantation, thus making it possible to clearly delimit the location of the PN junctions, and therefore the dimensions of the space charge areas, while using conventional implantation masks which can also be used for manufacturing non-volatile memories, without the need to provide strict alignment of these masks.

Furthermore, the implantation of the junctions up to the insulating layer makes it possible to suppress bipolar parasitic effects with the underlying substrate.

Although it would be possible to form implantations of the second type of conductivity, of the P-type for example, between each projecting region, so as to produce a series of diodes head to tail, it is particularly advantageous to alternate a P-type implantation with an N-type implantation, making it possible, notably, to form PN diodes which can readily be used in a Graetz bridge.

Thus, according to one embodiment, the method comprises a second implantation of dopants having a first type of conductivity, of the N-type for example, in the first semiconductor layer, so that the first implantation of dopants, of the P-type for example, and the second implantation of dopants, of the N+ type for example, define respectively, in the first semiconductor layer, first areas having the second type of conductivity (of the P+ type for example) overdoped relative to the rest of the first semiconductor layer, and second areas having the first type of conductivity (of the N+ type for example) overdoped relative to the rest of the first semiconductor layer, a first area lying between two second areas and separated from these two second areas by two interleaved regions of the first semiconductor layer located, respectively, under two neighboring projecting regions, each diode being formed at the junction between a first area and an interleaved region.

According to one embodiment, the first areas are of the P+ type of conductivity, forming the anodes of the diodes, the second areas are of the N+ type conductivity, forming the cathodes of the diodes together with the interleaved regions, and the method also comprises the forming of contacts on the first and second areas.

The insulating layer may be of the shallow trench type, and the first semiconductor layer may be formed by a deposit of polysilicon on the insulating layer and implantation by dopants having the first type of conductivity.

Advantageously, the projecting regions comprise a layer of dielectric surmounted by a gate material.

According to one embodiment, the forming of the first semiconductor layer is carried out simultaneously with the forming of floating gates of floating gate transistors, and the forming of the projecting regions is carried out simultaneously with the forming of control grids of the floating gate transistors.

According to another aspect, the invention proposes an integrated circuit comprising, on top of an insulating layer surmounting a semiconductor substrate, a first semiconductor layer having a first type of conductivity, projecting regions spaced apart from each other on the first semiconductor layer, and a sequence of PN junctions forming diodes, extending in the semiconductor layer to insulating layer at the edge of the projecting regions.

According to one embodiment, the integrated circuit comprises, in the first semiconductor layer, first areas having the second type of conductivity, overdoped relative to the rest of the first semiconductor layer, and second areas having the first type of conductivity, overdoped relative to the rest of the first semiconductor layer, a first area lying between two second areas and separated from these two second areas by two interleaved regions of the first semiconductor layer located, respectively, under two neighboring projecting regions, each diode being formed at the junction between a first area and an interleaved region forming a diode.

According to one embodiment, the first areas are of the P+ type of conductivity, forming the anodes of the diodes, the second areas are of the N+ type conductivity, forming the cathodes of the diodes together with the interleaved regions, and the first and second areas also comprise contacts on their surfaces.

The first semiconductor layer may be a layer of polysilicon.

The projecting regions may comprise a layer of dielectric surmounted by a gate material.

Advantageously, some of the diodes form a current bridge rectifier of the Graetz bridge type.

According to one embodiment, wherein the integrated circuit further comprises floating gate transistors each comprising a floating gate and a control gate, the first semiconductor layer is located at the same level as the floating gates of the floating gate transistors, and the projecting regions are located at the same level as the control gates of the floating gate transistors.

The integrated circuit may also comprise a non-volatile memory comprising the floating-gate transistors.

In other words, the various proposed modes of embodiment and construction relate to diodes completely insulated from the substrate. Consequently, no parasitic effect due to a PN junction between a doped region of the diode and the substrate can occur.

On the other hand, the various proposed modes of embodiment and construction have been developed, notably, to be fully compatible with the technological constraints of the use and manufacture of non-volatile memories, particularly non-volatile memories comprising floating gate transistors.

For example, the proposed modes of embodiment enable the diodes to be formed without adding any step, and notably without adding a step of masking which is critical in respect of alignment, to an ordinary method of manufacturing floating gate transistors.

Furthermore, the proposed modes of construction and embodiment are optimized for the technological field, notably as regards the control of the dopant diffusion areas.

The proposed solutions also make it possible to reduce the surface area occupied by the diodes.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and characteristics of the invention will be apparent from a perusal of modes of construction and embodiment of the invention, which are not limiting in any way, and the appended drawings, in which:

FIG. 1, described above, shows a conventional electronic circuit comprising a diode bridge,

FIG. 2 shows a sectional view of a mode of construction of an integrated circuit according to the invention, and

FIG. 3 shows an embodiment of a method according to the invention, and corresponds to a top view of the section of FIG. 2.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 2 is a sectional view of an integrated circuit comprising three diodes D₁, D₂, D₃ formed on a semiconductor substrate 1. The semiconductor substrate 1 may be, with reference to FIG. 1, the substrate PSUB itself or a box structure formed in the substrate, for example the box structure N-ISO, again with reference to FIG. 1.

Different manufacturing steps of a method for producing this structure will now be described with reference to FIGS. 2 and 3.

An insulating layer 3 has been formed on the surface of the substrate 1, for example, by a method similar to a conventional known method for forming a shallow insulating trench.

A first semiconductor layer 5, for example a layer of polysilicon doped with a first type of conductivity, of the N-type for example, is then formed on the insulating layer 3.

In a customary method for manufacturing non-volatile memories, this step can be executed jointly with a step of forming polysilicon floating gates of floating-gate transistors.

In the customary method for manufacturing non-volatile memories, control gates of the floating-gate transistors are then formed, usually comprising a layer of dielectric surmounted by a layer of polysilicon. The control gates are, for example, formed in strips extending in a direction orthogonal to the section plane of FIG. 2.

The control gates may also be formed from any other gate material, such as a metal.

Additionally, structures known as “dummies” are commonly added to the functional structures, notably in order to avoid breaks in periodicity which are harmful in some steps of the manufacture of integrated circuits, but they do not usually have any supplementary function.

In the method of forming the diodes D₁, D₂, D₃, a layer of dielectric 7 surmounted by a layer of polysilicon 9 is formed on the surface of the first polysilicon layer 5, forming projecting regions CGf on the surface of the first polysilicon layer.

The projecting regions CGf may advantageously be dummy control gates specified in the context of a method of manufacturing floating-gate transistors.

In this embodiment, the projecting regions CGf are used as a hard mask for forming implantations of dopants in the first polysilicon layer 5.

As illustrated in FIG. 3, the projecting regions CGf are arranged here in strips extending in a direction orthogonal to the section plane of FIG. 2, represented by the line II-II.

An implantation of dopants having the second type of conductivity (P+) is carried out along first implantation surfaces 10 so as to form first areas 11-11′ which are overdoped relative to the doping of the first polysilicon layer 5, for example by having a concentration which is higher by a factor of 100.

The implantation surfaces 10 cover the parts of the first polysilicon layer 5 located between two projecting regions CGf, and may overflow on to a portion of the strips of projecting regions CGf.

This is because, even if the implantation surfaces 10 are poorly aligned relative to a specified implantation surface (that is to say, the polysilicon surface 5 between two projecting regions CGf), the first resulting implanted areas 11-11′ will be delimited precisely and regularly by the edges bCGf of the projecting regions CGf.

Consequently, the implantation requires no supplementary critical masking step, particularly in a method including the forming of floating-gate transistors.

This permits a good degree of control of the implantation surfaces, and consequently the lateral distribution of the dopants in the polysilicon layer 5.

The regions of the first polysilicon layer 5 located under the projecting regions CGf are therefore not implanted, and form regions 12 called interleaved regions.

On the other hand, the thickness of the first polysilicon layer 5 and the depth of implantation of the dopants are advantageously designed to be such that the implantation 10 is diffused throughout the thickness of the first polysilicon layer 5, as far as the insulating layer 3.

As a result of the diffusion, the first areas 11-11′ comprise a very strongly doped region 11 close to the surface and a deeper less strongly doped region 11′, reaching the insulating layer 3.

Thus PN junctions between the first areas 11-11′ and the interleaved regions 12 extend to the insulating layer 3 and are located on the edges of the projecting regions bCGf in the first polysilicon layer 5.

Since the dopant implantations are not isotropic, the term “edges of the projecting regions” signifies a region adjacent, or close, to the geometric projection of the contour of the projecting regions in the first polysilicon layer 5.

Implantations of dopants having the first type of conductivity (N+) are carried out in a corresponding manner along second implantation surfaces 13 so as to form second areas 14-14′ which are overdoped relative to the doping of the first polysilicon layer 5.

The implantation surfaces 13 cover the parts of the first polysilicon layer 5 located between the edges bCGf of two projecting regions CGf, and may also overflow on to a portion of the projecting regions CGf.

Similarly, the thickness of the first polysilicon layer 5 and the depth of implantation of the dopants are advantageously designed to be such that the implantation is diffused throughout the thickness of the second polysilicon layer 5, forming a very strongly doped region 14 and a less strongly doped region 14′ reaching the insulating layer 3.

In this mode of construction and embodiment, one region out of every two regions located between two strips of projecting regions CGf is doped with the first type of conductivity, while the other is doped with the second type of conductivity.

The first areas 11-11′ form, with the interleaved regions 12 of the first polycrystalline silicon layer 5, PN junctions extending to the insulating layer 3.

Thus the first areas 11-11′ form anode regions and the second areas 14-14′ form, with the interleaved regions 12, cathode regions of diodes D₁, D₂, D₃ constructed in this way.

It is then possible to form, in a conventional manner, spacers 15 of a dielectric material placed on the sides of the projecting regions (or dummy control gates) CGf, and contact terminals for the cathodes 17 and anodes 19, for example by siliciding the surfaces of the anode and cathode regions which are not covered by the spacers 15 or the projecting regions CGf, on which metallic cathode contacts 21 and anode contacts 23 are respectively formed.

Thus diodes D₁, D₂, D₃ are produced, formed by a PN junction extending to the insulating layer 3, between an anode formed by a first overdoped area 11-11′ and a cathode formed by a second overdoped area 14-14′ and an interleaved region 12.

The diodes D₁, D₂, D₃ are therefore completely insulated from the semiconductor substrate 1.

Additionally, in this embodiment, at least one cathode region 14-14′ is common to two different diodes, for example the diodes D₁ and D₂, and lies between two respective anode regions 11-11′. Also, at least one anode region 11-11′ is common to two different diodes, for example the diodes D₂ and D₃, and lies between two respective cathode regions 14-14′.

This configuration with common electrodes is particularly advantageous for the construction of a diode bridge of the Graetz bridge type, having an anode node common to two diodes and a cathode node common to two diodes.

Furthermore, the invention is not limited to the present description, but embraces all variants thereof.

For example, it is feasible for the second implantation 13 to be an implantation of dopants having the second type of conductivity, in a similar manner to the first implantation 10, forming a series of diodes head to tail between the implanted areas and the interleaved areas, the various cathodes being electrically connectable via contacts extending in a plane other than the planes of the attached figures. 

What is claimed is:
 1. An integrated circuit comprising: a semiconductor substrate; an insulating layer overlying the semiconductor substrate; a semiconductor layer of a first conductivity type overlying the insulating layer; a plurality of projecting regions that are spaced apart from each other overlying the semiconductor layer; and a sequence of PN junctions in the semiconductor layer, each PN junction located at an edge of an associated projecting region and vertically extending from an upper surface of the semiconductor layer to the insulating layer.
 2. The integrated circuit according to claim 1, wherein the plurality of projecting regions comprises disconnected strips extending along a top surface of the semiconductor layer, the disconnected strips being parallel to each other.
 3. The integrated circuit according to claim 1, wherein the sequence of PN junctions forms a plurality of diodes, each diode including a heavily doped region of the first conductivity type that abuts a lightly doped region of the first conductivity type that abuts a doped region of a second conductivity type.
 4. The integrated circuit according to claim 3, wherein some of the diodes form a current bridge rectifier.
 5. The integrated circuit according to claim 4, wherein the current bridge rectifier comprises a Graetz bridge.
 6. The integrated circuit according to claim 1, wherein the sequence of PN junctions comprises first areas of a second conductivity type overdoped relative to other portions of the semiconductor layer, and second areas of the first conductivity type overdoped relative to the other portions of the semiconductor layer, a first area lying between two second areas and separated from these two second areas by two interleaved regions of the semiconductor layer located, respectively, under two neighboring projecting regions, each junction between a first area and an interleaved region forming a diode, wherein the first areas comprise P+ doped areas that form anodes of the diodes, and wherein the second areas comprise N+ doped areas that, together with the interleaved regions, form cathodes of the diodes.
 7. The integrated circuit according to claim 1, wherein the semiconductor layer is a polysilicon layer.
 8. The integrated circuit according to claim 1, wherein each of the plurality of projecting regions comprises a layer of dielectric and a gate material overlying the layer of dielectric.
 9. The integrated circuit according to claim 1, further comprising floating gate transistors laterally spaced from the sequence of PN junctions, each floating gate transistor comprising a floating gate and a control gate, wherein the semiconductor layer is located at the same level as the floating gates of the floating gate transistors, and the plurality of projecting regions is located at the same level as the control gates of the floating gate transistors.
 10. An integrated circuit comprising: a semiconductor substrate; an insulating layer overlying the semiconductor substrate; a semiconductor layer overlying the insulating layer; a plurality of projecting regions that are spaced apart from each other overlying the semiconductor layer; a plurality of interleaved regions disposed within the semiconductor layer, each interleaved region being located beneath an associated projecting region and being lightly doped with dopants of a first conductivity type; a plurality of first areas disposed within the semiconductor layer, each first area abutting an associated interleaved region at a location near a first edge of the associated projecting region, each first area being heavily doped with dopants of the first conductivity type and extending from an upper surface of the semiconductor layer to the insulating layer; and a plurality of second areas disposed within the semiconductor layer, each second area abutting an associated interleaved region at a location near a second edge of the associated projecting region, each second area being heavily doped with dopants of a second conductivity type and extending from the upper surface of the semiconductor layer to the insulating layer.
 11. The integrated circuit according to claim 10, wherein the plurality of projecting regions comprises disconnected strips extending along a top surface of the semiconductor layer, the disconnected strips being parallel to each other.
 12. The integrated circuit according to claim 10, wherein the interleaved regions, the plurality of first areas, and the plurality of second areas form diodes that are connected to form a current bridge rectifier.
 13. The integrated circuit according to claim 10, further comprising floating gate transistors laterally spaced from the plurality of projecting regions, each floating gate transistor comprising a floating gate and a control gate, wherein the semiconductor layer is located at the same level as the floating gates of the floating gate transistors, and the plurality of projecting regions are located at the same level as the control gates of the floating gate transistors.
 14. The integrated circuit according to claim 10, wherein the semiconductor layer is a polysilicon layer.
 15. The integrated circuit according to claim 10, wherein each of the plurality of projecting regions comprises a layer of dielectric and a gate material overlying the layer of dielectric.
 16. An integrated circuit comprising: a semiconductor substrate; an insulating layer overlying the semiconductor substrate; a first semiconductor region having a first conductivity type overlying the insulating layer, wherein the first semiconductor region has a first doping concentration; a second semiconductor region having the first conductivity type overlying the insulating layer, the second semiconductor region abutting the first semiconductor region, wherein the second semiconductor region has a second doping concentration that is less than the first doping concentration; a third semiconductor region having a second conductivity type overlying the insulating layer, the third semiconductor region abutting the second semiconductor region, wherein the second conductivity type is opposite the first conductivity type; a first PN junction at a first interface between the third semiconductor region and the second semiconductor region; a first conductive material overlying and electrically contacting the first semiconductor region; a second conductive material overlying and electrically insulated from the second semiconductor region; and a third conductive material overlying and electrically contacting the third semiconductor region.
 17. The integrated circuit according to claim 16, wherein the first conductive material and the third conductive material each comprise a metallic material.
 18. The integrated circuit according to claim 16, wherein the second conductive material comprises polysilicon.
 19. The integrated circuit according to claim 16, further comprising: a fourth semiconductor region having the first conductivity type overlying the insulating layer, the fourth semiconductor region abutting the third semiconductor region, wherein the fourth semiconductor region has a third doping concentration substantially equal to the second doping concentration; and a second PN junction at a second interface between the fourth semiconductor region and the third semiconductor region.
 20. The integrated circuit according to claim 19, further comprising: a fourth conductive material overlying and electrically insulated from the fourth semiconductor region. 